This invention relates to a logical device test system for testing logical devices such as, for example, a microprocessor, a semiconductor memory, a semiconductor integrated circuit composed of logical circuits and so forth.
In a system for testing of this kind, logical input patterns composed of various logical values, corresponding to a plurality of terminals of the device under test, are applied thereto, and the outputs, i.e. output patterns derived from a plurality of output terminals of the device under test, are compared with expected value patterns which are to be obtained when the device under test operates normally, thereby checking whether the logical element operates normally or not. In this case, if the logical device under test is one having complicated functions, for example, a microcomputer, it is necessary to conduct various tests by applying a number of input patterns to the logical device under test. In the prior art, the input patterns and the expected value patterns corresponding thereto are prestored in a pattern file, the input patterns are successively read therefrom to be input to the logical device under test, and the resulting output patterns therefrom are respectively compared with the expected value patterns. In the conventional equipment, the required test pattern storage capacity for the input patterns and the expected value patterns, is enormous.
Also in the past, attempts have been made to reduce the required storage capacity of the pattern file for storing the test patterns. A series of test patterns, which can be successively read out, includes those of the so-called pattern pause test, which repeatedly applies the same input pattern to the logical device under test a plurality of times, and the pattern loop test which repeatedly applies a plurality of successive input pattern groups to the logical device under test. In such a case, the following method has been adopted for reducing the storage capacity for the test patterns: Namely, in the pattern loop test, leading and last addresses of the pattern loop are prestored in a register, and the number of times of looping is also prestored in another register. When the content of a program counter for the pattern file having stored therein the test patterns coincides with the last address of the loop stored in the register, the coincidence is detected, and the content of the program counter is set at the leading address of the loop stored in the register, and one is subtracted from the content of the register having stored therein the number of times of looping; these operations are repeatedly carried out to repeat reading of each address between the leading and the last addresses the preset number of times. To this end, there is inserted in the program of the test pattern a program for writing the leading and last addresses of the pattern loop test and the number of times of looping in registers. While they are written in the registers, the test of the logical device under test is interrupted, and this period of interruption idles to the logical device under test; that is, the so-called dummy cycle occurs. In the case of conducting the pattern pause test, a program for writing the address therefor and the number of pattern pauses in registers is inserted in the program of the test pattern, and they are written in the registers by executing the program, so that during the execution, a dummy cycle occurs. The occurrence of such a dummy cycle sometimes causes not only an increase in the test time but also a change in the state of the logical device under test during the dummy cycle in the case of some particular logical devices, resulting in the test becoming incorrect.
Accordingly, it is an object of this invention to provide a logical device test system which permits a pattern loop test, a pattern pause test or more complicated tests without generation of a dummy cycle.
Conventional test systems of this type may in some cases repeat the same test step while modifying one part of the control procedure for the test. For example, in the case of adding together two data to obtain the result of addition, it happens sometimes to repeat the test while successively modifying only one of the data; in this case, only one of the data is modified, but the other data is held unchanged. In the prior art, however, even in the case of repeating the same test patterns, if the data (pattern) of its address is altered, no pattern test can be conducted, and to avoid this, these same patterns are sequentially stored in a pattern file; therefore, the storage capacity of the pattern file is required to be large.
Another object of this invention is to provide a logical device test system in which is the case of substantially the same test patterns being repeated, both invariable fixed test patterns and variable test patterns modified for each cycle of the test are stored, thereby reducing the required storage capacity of the pattern file.
Another object of this invention is to provide a logical device test system which permits the insertion of a test pattern of a variable content in fixed test patterns.
In some logical devices under test, the test operation cannot be allowed to proceed until their output reach a certain state; in the test of this type of the logical device, such an arrangement is made that, if the output pattern from the logical device under test and the expected value pattern therefore are not detected coincident, the test operation does not proceed to the next step. In this case, when coincidence is detected between the output pattern from a predetermined one of the output terminals of the logical device under test and the expected value pattern corresponding thereto, the test is permitted to proceed to the next step, and in addition, designation of the output terminal is modified. In the prior art, data for designating the output terminal of the logical device under test to be checked for coincidence with the expected value pattern, that is, the so-called mask data is stored in the pattern file at the same addresses as those from which the test patterns are read out; namely, a storage area for the mask data is always provided in each address of the pattern file. Accordingly, the pattern file is required to have a storage capacity for the number of bits of the mask data and the number of addresses of the pattern file, resulting in an appreciably large storage capacity.
In such a test in which the test operation proceeds to the next step only after coincidence is detected between the output pattern from the logical device under test and the expected value pattern, there is a possible further requirement that the test operation proceeds to the next step not merely if the case of the coincidence being detected once but only if is also detected in each of a plurality of succeeding test steps, that is, in the case of the output patterns from the logical device being detected coincident with predetermined patterns in the direction in which the test steps proceed. For conducting such a test, in the prior art, expected value patterns in the direction of the test step proceeding are stored in a register, and the outputs from the logical device under test for respective steps are sequentially applied to a shaft register, and coincidence is detected between the contents of the two registers. Such coincidence detection is needed for each of predetermined output terminals, resulting in an increased amount of hardware.
Another object of this invention is to provide a logical device test equipment in which, when performing a coincidence detecting test in the direction of progress of the test, the depth of the output pattern (i.e. its length on the sequential direction) can freely be altered to provide for enhanced flexibility and to enable a complicated test.
Another object of this invention is to provide a logical device test system which permits easy designation of output terminals and enables a required test with a small storage capacity for mask data for the output terminal designation.
In order to locate malfunction of the logical device under test or analyze the cause of malfunction in the case of non-coincidence between the output pattern from the logical device under test and the expected value pattern, a compared pattern indicating the compared result is stored in the so-called fail memory, and after completion of the test, the stored result is read out and analyzed using the input pattern corresponding thereto. Since only compared patterns at the time of non-coincidence are stored in the fail memory, the compared patterns must be coordinated with the input patterns, and this coordination is relatively complicated. Further, the provision of the fail memory for the above purpose increases the amount of hardware required. Moreover, the compared patterns stored in the fail memory are those obtained only in connection with predetermined output terminals of the logical device under test, so that the so-called mask data is employed. In the prior art, the mask data is stored in the pattern file at each address; therefore, the storage capacity for the mask data is large.
Another object of this invention is, therefore, to provide a logical device test system which is capable of storing compared patterns without the necessity of specially providing a fail memory, and which readily provides the coordination between the stored compared patterns and input patterns, thereby facilitating an analysis of the test result.
Another object of this invention is to provide a logical device test system which is capable of storing, with a small storage capacity, mask data for taking out compared patterns at designated output terminals respectively corresponding thereto when storing the compared patterns.
In the prior art, output patterns which are derived from an accepted logical device under test by successively applying input patterns are used as expected value patterns, and these expected value patterns are sequentially written in the pattern file at the addresses of the input patterns corresponding to them. In this case, since the output terminals at which the output patterns are provided vary with test steps, the output patterns are written in all bits of each address of the pattern file. In other words, the output patterns are written in those areas of the pattern file in which the input patterns are already written; consequently, the input patterns are erased, and it is necessary to re-write the corresponding input patterns in the pattern file from the outside after storing of the expected value patterns. Therefore, it takes a relatively much time to obtain test patterns composed of input and expected value patterns in pairs.
Another object of this invention is to provide a logical device test system which is capable of writing expected value patterns in the pattern file without erasing input patterns corresponding thereto, and hence is able to provide test patterns in a short time and to reduce the time for the so-called copy.
Some logical devices under test use their terminals both as input and output terminals on a time-shared basis. A method that has been employed for testing such logical devices is as follows: Prior to applying input patterns to the logical device under test, input/output control data indicating which terminals of the logical device are used as input and output terminals respectively and, if necessary, mask data representing which one of the designated terminals is required, with the other terminals ignored, are respectively read from the pattern file one by one for each step of the program counter, and are stored in an input/output control register and a mask register. After completion of storing of these data, each terminal of the logical device under test is controlled by the input/output control data to act as an input or output terminal, and the mask data determine whether the terminal is to be ignored or not; in such a state, the input patterns are each applied to the logical device under test, and the output pattern therefrom and the expected value pattern corresponding thereto are compared. In this case, since one step of the program counter is used for reading out each of the input/output control data and the mask data, no test is conducted in this period, resulting in a dummy cycle. Some kinds of logical devices change their output status during such dummy cycle and hence cannot correctly be tested. Further, it is necessary to increase the speed of the operation cycle of the pattern file twice or three times as high as the operation cycle of the logical device under test; this increases the cost of the equipment.
Still another object of this invention is to provide a logical device test system which is capable of producing, without occurrence of a dummy cycle, input/output control data for a logical device having input/output terminals and, if necessary, mask data for determining whether data of a designated one of the terminals is to be considered or ignored, and which is able to reduce the required storage capacity for these data and hence is inexpensive accordingly.